1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device that has a current conductive state and a cut off state realized according to the voltage of a gate electrode.
2. Description of the Background Art
A lateral type IGBT (Insulated Gate Bipolar Transistor) will be described hereinafter with reference to the drawings as a first example of a conventional semiconductor device. An IGBT is used for the control of electric motors and the like that require high voltage and high current. FIG. 19 is a perspective view showing such a conventional IGBT in a bird's eye view, and FIG. 20 is a sectional view taken along line XX--XX of FIG. 19.
Referring to FIGS. 19 and 20, a buried oxide 2 film is formed on a semiconductor substrate 1. An n.sup.- layer 3 is formed on buried oxide film 2. A p channel MOS transistor 5 is formed on the surface of n.sup.- layer 3. P channel MOS transistor 5 includes a p.sup.- diffusion region 7, a p.sup.+ diffusion region 9, and a gate electrode 11.
An n.sup.+ diffusion region 13 is formed adjacent p.sup.+ diffusion region 9. An n well 15 is formed so as to surround p.sup.+ diffusion region 9 and n.sup.+ diffusion region 13. A source electrode 17 is formed so as to be electrically connected to p.sup.+ and n.sup.+ diffusion regions 9 and 13. Source electrode 17 extends above gate electrode 19 and p.sup.- diffusion region 7 with an oxide film 19 thereunder.
A p.sup.+ diffusion region 23 is formed continuously to one end of p.sup.- diffusion region 7. An n.sup.+ diffusion region 21 is formed so as to be surrounded by p.sup.+ diffusion region 23. A drain electrode 25 is formed electrically connected to n.sup.+ diffusion region 21 and p.sup.+ diffusion region 23. A substrate electrode (back electrode) 27 is formed at the back side of semiconductor substrate 1.
The operation of IGBT will be described hereinafter. First, an off operation will be described with reference to FIGS. 21 and 22 indicating the state of a depletion layer in an off operation of IGBT in a step manner. Referring to FIGS. 21 and 22, the potential of drain electrode 25 and substrate electrode 27 are 0 V, and a positive potential (+V) is applied to gate electrode 11 and source electrode 17.
As a result, a depletion layer expands from a pn junction J1 at the interface of p.sup.- diffusion region 7 and n.sup.- layer 3, and from a pn junction J2 at the interface between p.sup.+ diffusion region 23 and n.sup.- layer 3. The depletion layer expanding from pn junction J1 also expands towards p.sup.- diffusion region 7 as well as toward n.sup.- layer 3 since p.sup.- diffusion region 7 is a region of low concentration. Therefore, p.sup.- diffusion region 7 is also partially depleted. Source electrode 17 formed overlying p.sup.- diffusion region 7 constitutes a field plate. Accordingly, the depletion of p.sup.- diffusion region 7 is promoted to relax the electric field at the neighborhood of gate electrode 11 of pn junction J1.
At the same time, a depletion layer begins to expand from an interface J3 between n.sup.- layer 3 and buried oxide film 2. This expansion of a depletion layer relaxes the electric field at the neighborhood of each pn junction. By further applying a high positive potential, n.sup.- layer 3 and p.sup.- diffusion region 7 are partially depleted. Thus, an off state can be maintained.
An on operation will be described hereinafter with reference to FIG. 23. The potential of gate electrode 11 is set lower than the potential of source electrode 17. This causes the surface of n.sup.- layer 3 right beneath gate electrode 11 to be inverted to the p type to form a channel region. As a result, hole current 28a flows from p.sup.+ diffusion region 9 to p.sup.+ diffusion region 23 via the channel region and p.sup.- diffusion region 7.
Hole current 28a arriving at p.sup.+ diffusion region 23 flows to drain electrode 25 through a pinch resistance area generated at the interface between n.sup.+ diffusion region 21 and p.sup.+ diffusion region 23. By the voltage drop due to pinch resistance, a potential difference is generated between n.sup.+ diffusion region 21 and p.sup.+ diffusion region 23. When the hole current increases and the potential difference arrives at a certain level, modulation in conductivity occurs. As a result, electron current 28b begins to flow from n.sup.+ diffusion region 21 towards p.sup.+ region 7 and n.sup.+ layer 3. Thus, an on state is realized.
Another example of a conventional IGBT disclosed in Japanese Patent Laying-Open No. 4-2169 will be described hereinafter. FIG. 24 is a sectional view of this IGBT, and FIG. 25 is a plan view of the neighborhood of the drain electrode shown in FIG. 24.
Referring to FIGS. 24 and 25, an n.sup.- type semiconductor layer 112 is grown epitaxially on a p.sup.- type semiconductor substrate 111. A p.sup.+ type buried layer 113 and an isolation region 114 are formed at n.sup.- semiconductor layer 112. A p type base region 115 is formed at a surface portion of n.sup.- type semiconductor layer 112.
An n.sup.+ source region 116 is selectively formed at a portion of p type base region 115. A gate electrode 117 is formed at the surface of p type base region 115 sandwiched between n.sup.+ source region 116 and n.sup.- semiconductor layer 112 with a gate insulation film 118 thereunder. A source electrode 119 is formed at the surface of n.sup.+ source region 116.
An n type buffer region 120 having a continuous curve is spaced apart from p type base region 115 at the surface of n.sup.- type semiconductor layer 112. A p.sup.+ type drain region 121 is formed in an n type buffer region 120. P.sup.+ type drain region 121 has both side portions conforming to the curve configuration.
P.sup.+ type drain region 121 includes parallel regions 121a, 121a. An n.sup.+ type contact region 122 is formed between parallel regions 121a, 121a. A drain electrode 123 is formed electrically connected to region 121a and n.sup.+ contact region 122.
The operation of this second conventional IGBT will be described hereinafter. By applying a voltage exceeding the threshold value to gate electrode 117, an inversion layer is formed at the surface of p type base region 115. An electron current flows from n.sup.+ type source region 116 towards n.sup.- semiconductor layer 112 through this inversion layer.
The electrons flowing to n.sup.+ type semiconductor layer 112 flows in n type buffer region 120 establishing low resistance. Since n type buffer region 120 and p.sup.+ drain region 121 have a curved configuration, electrons will flow through a distance longer than that of a linear configuration. This means that a greater voltage drop is obtained by a smaller current. As a result, modulation in conductivity occurs even with a relatively low current to maintain the IGBT at an on state.
In the above-described first IGBT, the resistance of p.sup.- diffusion region 7 is the main factor that determines the resistance of the IGBT at the transition to an on operation. It is therefore desirable to reduce the resistance of this p.sup.- diffusion region 7 to conduct greater current at an on operation. A general approach to reduce the resistance of p.sup.- diffusion region 7 is to increase the p type impurity concentration.
However, increase in the p type impurity region in p.sup.- diffusion region 7 will suppress expansion of the depletion layer from pn junction J1 towards p.sup.- diffusion region 7. The depletion layer end E at drain electrode 25 side shown in FIG. 22 will be located closer to source electrode 17. This induces the problem that the breakdown voltage between source electrode 17 and drain electrode 25 is reduced.
In an on operation, the hole current flows from p.sup.+ diffusion region 9 to p.sup.- diffusion region 7 through the channel region. The hole current flowing to p.sup.- diffusion region 7 passes through p.sup.+ diffusion region 23 beneath n.sup.+ diffusion region 21 to arrive at drain region 25. A short-circuit plane 26 to p.sup.- diffusion region 7, n.sup.+ diffusion region 21, and drain electrode 25 has a plane structure shown in FIG. 19 or 26.
Therefore, the hole current flows substantially in a linear manner to short-circuit plane 26 as indicated by arrow 29 in FIG. 29. More specifically, the hole current flows so as to further reduce the voltage drop generated by pinch resistance 30 occurring at the interface of n.sup.+ diffusion region 21 and p.sup.+ diffusion region 23, as shown in FIGS. 26 and 27.
A sufficient potential difference between n.sup.+ diffusion region 21 and p.sup.+ region 23 cannot be established, so that there is not much electron current flowing from n.sup.+ diffusion region 21 to p.sup.+ diffusion region 23. It is therefore difficult to increase the current (on driving current) at an on state.
In the second conventional IGBT, an n-chMOS transistor is applied. A case is considered where a p-chMOS transistor is applied to the IGBT of this structure. It is easily conceived of substituting a p.sup.- layer for n.sup.- layer 3 to form a predetermined diffusion region. However, it is difficult to form an n type impurity region at a p.sup.- layer due to fabrication reasons such as diffusion is extremely time consuming.
Therefore, a predetermined diffusion region is formed respectively at the surface of n.sup.- layer 112 as shown in FIG. 28. Particularly, a p type buffer region 220 having a continuous curved configuration is formed spaced apart from n type base region 215. An n.sup.+ type drain region 221 is formed within p type buffer region 220. N.sup.+ type drain region 221 includes a parallel region 221a. A p.sup.+ type contact region 222 is formed at parallel region 221a. The curved p type buffer region 220 is formed closer to the source side so that the p channel has a predetermined length. This means that the distance between the end of the depletion layer expanding from pn junction J4 and the end of the depletion layer expanding from pn junction J5 becomes shorter. This induces the problem that the breakdown voltage of the IGBT is reduced.
To compensate for this problem, an approach is considered of reducing the impurity concentration of the p type buffer region to promote the expansion of the depletion layer to the p type buffer region. However, a problem occurs in which the depletion layer expanding from the p type buffer region comes into contact with the n type drain region to cause punch through. Eventually, the breakdown voltage of the IGBT cannot be improved.
As described above, it was difficult to increase the breakdown voltage in an off operation and also increase the on driving current in an on operation in a conventional IGBT.